1. Field
The following description relates to a pipeline processor, and more particularly, to interrupt handling for an equal-model processor.
2. Description of the Related Art
A pipeline processor processes an instruction with multiple operations, for example, fetching, decoding, execution, write-back, and the like. As a pipeline processor can execute a plurality of instructions, including when the instructions overlap with each other during the multiple operations, the pipeline processor can achieve a relatively high-speed processing of instructions.
Pipeline processors include an equal-model processor and a Less-Than-or-Equal (LTE)-model processor. In both an equal-model processor and an LTE-model processor, maximum latencies for instructions are implemented. The maximum latency of each instruction varies depending on the type of processor. A compiler of the processor discerns the maximum latency of each instruction, and schedules the instruction according to, in part, the maximum latency.
The term ‘maximum latency’ is described as the upper limit of an amount of time for executing an operation corresponding to an instruction and writing the result of the execution in a target register. In an equal-model processor, the execution result of an instruction is written in a target register only after the maximum latency has elapsed. However, in an LTE-model processor, the execution result of an instruction may be written in a target register before the maximum latency elapses.
Accordingly, an equal-model processor provides flexible scheduling through multiple allocations of registers, since the execution results of instructions are not written in target registers until the maximum latencies elapse. However, an LTE-model processor is limited with respect to multiple allocations of registers, since the execution results of instructions may be written in target registers before the maximum latencies elapse.
In order for an equal-model processor to process an interrupt every cycle, a relatively complicated algorithm or apparatus is required. More specifically, an equal-model processor schedules instructions according to, in part, the maximum latencies of the instructions. When is handling an interrupt while processing scheduled instructions, the processing of the scheduled instructions is delayed by the amount of time used to handle the interrupt. Here, the scheduled instruction may be an instruction scheduled according to an assumption that the execution result of the previous instruction has yet not been reflected. If the latency of the previous instruction elapses while the interrupt is processed, the value of the corresponding target register may be changed. If an instruction scheduled according to the assumption that the execution result of the previous instruction has not yet been reflected is received, an erroneous execution may occur when the received instruction is executed. Accordingly, a relatively complicated apparatus for preventing such erroneous execution may be needed in order for the equal-model processor to handle interrupts every cycle.
In order to prevent programs from operating erroneously in an equal-model processor, a method has been proposed to allow processing of an interrupt only with respect to specific instructions. A conventional method provides processing of an interrupt only when processing instructions that do not to cause errors during execution of the instructions, such as erroneous execution when interrupts are processed. The conventional method reduces erroneous execution of programs by allowing processing of an interrupt only when processing specific instructions, such as a branch instruction, scheduled according to an assumption that the maximum latency of the previous instruction has elapsed.
The conventional method helps reduce erroneous execution, but includes a disadvantage in that it cannot quickly process an interrupt and further may not be able to process any interrupt for an extended period of time. Instructions that are unlikely to cause errors when an interrupt is processed during execution of instructions are limited to only certain instruction types, such as ‘branch’, ‘jump’, and ‘function-call’. As a result of this limitation, it is possible that an interrupt is not processed for several hundreds or thousands of cycles. Moreover, since most is interrupts require prompt processing, a long time delay may deteriorate the performance of the processor.